10 #if FW_ENABLE_TEXT_LOGGING
32 this->m_CycleIn_InputPort[port].
init();
37 this->m_CycleIn_InputPort[port].
setPortNum(port);
39 #if FW_OBJECT_NAMES == 1
43 this->m_objName.toChar(),
46 this->m_CycleIn_InputPort[port].setObjName(portName.
toChar());
56 this->m_Time_OutputPort[port].
init();
58 #if FW_OBJECT_NAMES == 1
62 this->m_objName.toChar(),
65 this->m_Time_OutputPort[port].setObjName(portName.
toChar());
75 this->m_Tlm_OutputPort[port].
init();
77 #if FW_OBJECT_NAMES == 1
81 this->m_objName.toChar(),
84 this->m_Tlm_OutputPort[port].setObjName(portName.
toChar());
94 this->m_RateGroupMemberOut_OutputPort[port].
init();
96 #if FW_OBJECT_NAMES == 1
100 this->m_objName.toChar(),
103 this->m_RateGroupMemberOut_OutputPort[port].setObjName(portName.
toChar());
120 return &this->m_CycleIn_InputPort[portNum];
138 this->m_Time_OutputPort[portNum].
addCallPort(port);
170 this->m_RateGroupMemberOut_OutputPort[portNum].
addCallPort(port);
173 #if FW_PORT_SERIALIZATION
182 Fw::InputSerializePort* port
190 this->m_Time_OutputPort[portNum].registerSerialPort(port);
196 Fw::InputSerializePort* port
204 this->m_Tlm_OutputPort[portNum].registerSerialPort(port);
209 #if FW_PORT_SERIALIZATION
218 Fw::InputSerializePort* port
226 this->m_RateGroupMemberOut_OutputPort[portNum].registerSerialPort(port);
237 Fw::PassiveComponentBase(compName)
240 this->m_first_update_MaxCycleTime =
true;
241 this->m_last_MaxCycleTime = 0;
298 return this->m_Time_OutputPort[portNum].
isConnected();
309 return this->m_Tlm_OutputPort[portNum].
isConnected();
324 return this->m_RateGroupMemberOut_OutputPort[portNum].
isConnected();
366 this->m_RateGroupMemberOut_OutputPort[portNum].
invoke(
382 if (not this->m_first_update_MaxCycleTime) {
384 if (arg == this->m_last_MaxCycleTime) {
388 this->m_last_MaxCycleTime = arg;
392 this->m_first_update_MaxCycleTime =
false;
393 this->m_last_MaxCycleTime = arg;
396 if (this->m_Tlm_OutputPort[0].isConnected()) {
398 this->m_Time_OutputPort[0].isConnected() &&
401 this->m_Time_OutputPort[0].
invoke(_tlmTime);
415 this->m_Tlm_OutputPort[0].
invoke(
429 if (this->m_Tlm_OutputPort[0].isConnected()) {
431 this->m_Time_OutputPort[0].isConnected() &&
434 this->m_Time_OutputPort[0].
invoke(_tlmTime);
448 this->m_Tlm_OutputPort[0].
invoke(
462 if (this->m_Tlm_OutputPort[0].isConnected()) {
464 this->m_Time_OutputPort[0].isConnected() &&
467 this->m_Time_OutputPort[0].
invoke(_tlmTime);
481 this->m_Tlm_OutputPort[0].
invoke(
496 if (this->m_Time_OutputPort[0].isConnected()) {
498 this->m_Time_OutputPort[0].
invoke(_time);
510 void PassiveRateGroupComponentBase ::
#define FW_NUM_ARRAY_ELEMENTS(a)
number of elements in an array
#define PRI_PlatformIntType
@ TB_NONE
No time base has been established.
PlatformAssertArgType FwAssertArgType
PlatformIndexType FwIndexType
void init()
Object initializer.
const char * toChar() const
void addCallPort(InputTimePort *callPort)
Register an input port.
void invoke(Fw::Time &time)
Invoke a port interface.
void init()
Initialization function.
void addCallPort(InputTlmPort *callPort)
Register an input port.
void init()
Initialization function.
void invoke(FwChanIdType id, Fw::Time &timeTag, Fw::TlmBuffer &val)
Invoke a port interface.
SerializeStatus serialize(U8 val)
serialize 8-bit unsigned int
void format(const CHAR *formatString,...)
write formatted string to buffer
void init()
Initialization function.
void addCallPort(InputSchedPort *callPort)
Register an input port.
void invoke(U32 context)
Invoke a port interface.
Auto-generated base for PassiveRateGroup component.
PassiveRateGroupComponentBase(const char *compName="")
Construct PassiveRateGroupComponentBase object.
void tlmWrite_CycleTime(U32 arg, Fw::Time _tlmTime=Fw::Time())
void set_Tlm_OutputPort(FwIndexType portNum, Fw::InputTlmPort *port)
Connect port to Tlm[portNum].
bool isConnected_RateGroupMemberOut_OutputPort(FwIndexType portNum)
FwIndexType getNum_Time_OutputPorts() const
void set_Time_OutputPort(FwIndexType portNum, Fw::InputTimePort *port)
Connect port to Time[portNum].
virtual ~PassiveRateGroupComponentBase()
Destroy PassiveRateGroupComponentBase object.
bool isConnected_Tlm_OutputPort(FwIndexType portNum)
void set_RateGroupMemberOut_OutputPort(FwIndexType portNum, Svc::InputSchedPort *port)
Connect port to RateGroupMemberOut[portNum].
void tlmWrite_CycleCount(U32 arg, Fw::Time _tlmTime=Fw::Time())
void RateGroupMemberOut_out(FwIndexType portNum, U32 context)
Invoke output port RateGroupMemberOut.
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
FwIndexType getNum_Tlm_OutputPorts() const
void tlmWrite_MaxCycleTime(U32 arg, Fw::Time _tlmTime=Fw::Time())
FwIndexType getNum_RateGroupMemberOut_OutputPorts() const
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
bool isConnected_Time_OutputPort(FwIndexType portNum)
@ CHANNELID_MAXCYCLETIME
Channel ID for MaxCycleTime.
@ CHANNELID_CYCLETIME
Channel ID for CycleTime.
@ CHANNELID_CYCLECOUNT
Channel ID for CycleCount.
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
FwIndexType getNum_CycleIn_InputPorts() const
SerializeStatus
forward declaration for string
@ FW_SERIALIZE_OK
Serialization/Deserialization operation was successful.