RateGroupDriverComponentAc.cpp

Go to the documentation of this file.

// ======================================================================
// \title  RateGroupDriverComponentAc.cpp
// \author Generated by fpp-to-cpp
// \brief  cpp file for RateGroupDriver component base class
// ======================================================================
 
#include "F-Prime/Svc/RateGroupDriver/RateGroupDriverComponentAc.hpp"
#include "Fw/Types/Assert.hpp"
#include "Fw/Types/ExternalString.hpp"
#if FW_ENABLE_TEXT_LOGGING
#include "Fw/Types/String.hpp"
#endif
 
namespace Svc {
 
  // ----------------------------------------------------------------------
  // Component initialization
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    init(FwEnumStoreType instance)
  {
    // Initialize base class
    Fw::PassiveComponentBase::init(instance);
 
    // Connect input port CycleIn
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_CycleIn_InputPorts());
      port++
    ) {
      this->m_CycleIn_InputPort[port].init();
      this->m_CycleIn_InputPort[port].addCallComp(
        this,
        m_p_CycleIn_in
      );
      this->m_CycleIn_InputPort[port].setPortNum(port);
 
#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_CycleIn_InputPort[%" PRI_PlatformIntType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_CycleIn_InputPort[port].setObjName(portName.toChar());
#endif
    }
 
    // Connect output port CycleOut
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_CycleOut_OutputPorts());
      port++
    ) {
      this->m_CycleOut_OutputPort[port].init();
 
#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_CycleOut_OutputPort[%" PRI_PlatformIntType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_CycleOut_OutputPort[port].setObjName(portName.toChar());
#endif
    }
  }
 
  // ----------------------------------------------------------------------
  // Getters for typed input ports
  // ----------------------------------------------------------------------
 
  Svc::InputCyclePort* RateGroupDriverComponentBase ::
    get_CycleIn_InputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      portNum < this->getNum_CycleIn_InputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
 
    return &this->m_CycleIn_InputPort[portNum];
  }
 
  // ----------------------------------------------------------------------
  // Connect typed input ports to typed output ports
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    set_CycleOut_OutputPort(
        FwIndexType portNum,
        Svc::InputCyclePort* port
    )
  {
    FW_ASSERT(
      portNum < this->getNum_CycleOut_OutputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
 
    this->m_CycleOut_OutputPort[portNum].addCallPort(port);
  }
 
#if FW_PORT_SERIALIZATION
 
  // ----------------------------------------------------------------------
  // Connect serial input ports to typed output ports
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    set_CycleOut_OutputPort(
        FwIndexType portNum,
        Fw::InputSerializePort* port
    )
  {
    FW_ASSERT(
      portNum < this->getNum_CycleOut_OutputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
 
    this->m_CycleOut_OutputPort[portNum].registerSerialPort(port);
  }
 
#endif
 
  // ----------------------------------------------------------------------
  // Component construction and destruction
  // ----------------------------------------------------------------------
 
  RateGroupDriverComponentBase ::
    RateGroupDriverComponentBase(const char* compName) :
      Fw::PassiveComponentBase(compName)
  {
 
  }
 
  RateGroupDriverComponentBase ::
    ~RateGroupDriverComponentBase()
  {
 
  }
 
  // ----------------------------------------------------------------------
  // Getters for numbers of typed input ports
  // ----------------------------------------------------------------------
 
  FwIndexType RateGroupDriverComponentBase ::
    getNum_CycleIn_InputPorts() const
  {
    return static_cast<FwIndexType>(FW_NUM_ARRAY_ELEMENTS(this->m_CycleIn_InputPort));
  }
 
  // ----------------------------------------------------------------------
  // Getters for numbers of typed output ports
  // ----------------------------------------------------------------------
 
  FwIndexType RateGroupDriverComponentBase ::
    getNum_CycleOut_OutputPorts() const
  {
    return static_cast<FwIndexType>(FW_NUM_ARRAY_ELEMENTS(this->m_CycleOut_OutputPort));
  }
 
  // ----------------------------------------------------------------------
  // Connection status queries for typed output ports
  // ----------------------------------------------------------------------
 
  bool RateGroupDriverComponentBase ::
    isConnected_CycleOut_OutputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      portNum < this->getNum_CycleOut_OutputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
 
    return this->m_CycleOut_OutputPort[portNum].isConnected();
  }
 
  // ----------------------------------------------------------------------
  // Port handler base-class functions for typed input ports
  //
  // Call these functions directly to bypass the corresponding ports
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    CycleIn_handlerBase(
        FwIndexType portNum,
        Svc::TimerVal& cycleStart
    )
  {
    // Make sure port number is valid
    FW_ASSERT(
      portNum < this->getNum_CycleIn_InputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
 
    // Call handler function
    this->CycleIn_handler(
      portNum,
      cycleStart
    );
  }
 
  // ----------------------------------------------------------------------
  // Invocation functions for typed output ports
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    CycleOut_out(
        FwIndexType portNum,
        Svc::TimerVal& cycleStart
    )
  {
    FW_ASSERT(
      portNum < this->getNum_CycleOut_OutputPorts(),
      static_cast<FwAssertArgType>(portNum)
    );
    this->m_CycleOut_OutputPort[portNum].invoke(
      cycleStart
    );
  }
 
  // ----------------------------------------------------------------------
  // Calls for messages received on typed input ports
  // ----------------------------------------------------------------------
 
  void RateGroupDriverComponentBase ::
    m_p_CycleIn_in(
        Fw::PassiveComponentBase* callComp,
        FwIndexType portNum,
        Svc::TimerVal& cycleStart
    )
  {
    FW_ASSERT(callComp);
    RateGroupDriverComponentBase* compPtr = static_cast<RateGroupDriverComponentBase*>(callComp);
    compPtr->CycleIn_handlerBase(
      portNum,
      cycleStart
    );
  }
 
}