7 #ifndef Svc_ActiveRateGroupComponentAc_HPP
8 #define Svc_ActiveRateGroupComponentAc_HPP
14 #if FW_ENABLE_TEXT_LOGGING == 1
125 #if FW_ENABLE_TEXT_LOGGING == 1
128 void set_LogText_OutputPort(
165 #if FW_PORT_SERIALIZATION
176 Fw::InputSerializePort* port
179 #if FW_ENABLE_TEXT_LOGGING == 1
182 void set_LogText_OutputPort(
184 Fw::InputSerializePort* port
192 Fw::InputSerializePort* port
198 Fw::InputSerializePort* port
203 #if FW_PORT_SERIALIZATION
214 Fw::InputSerializePort* port
220 Fw::InputSerializePort* port
233 const char* compName =
""
266 #if FW_ENABLE_TEXT_LOGGING == 1
314 #if FW_ENABLE_TEXT_LOGGING == 1
319 bool isConnected_LogText_OutputPort(
504 static void m_p_CycleIn_in(
511 static void m_p_PingIn_in(
538 #if FW_ENABLE_TEXT_LOGGING == 1
570 bool m_first_update_RgMaxTime;
573 bool m_first_update_RgCycleSlips;
582 U32 m_last_RgMaxTime;
585 U32 m_last_RgCycleSlips;
PlatformSizeType FwSizeType
PlatformIndexType FwIndexType
C++-compatible configuration header for fprime configuration.
void init()
Object initializer.
Auto-generated base for ActiveRateGroup component.
FwIndexType getNum_Log_OutputPorts() const
FwIndexType getNum_PingIn_InputPorts() const
@ NUM_LOGTEXT_OUTPUT_PORTS
void tlmWrite_RgMaxTime(U32 arg, Fw::Time _tlmTime=Fw::Time())
void set_PingOut_OutputPort(FwIndexType portNum, Svc::InputPingPort *port)
Connect port to PingOut[portNum].
FwIndexType getNum_Time_OutputPorts() const
bool isConnected_Tlm_OutputPort(FwIndexType portNum)
void tlmWrite_RgCycleSlips(U32 arg, Fw::Time _tlmTime=Fw::Time())
FwIndexType getNum_CycleIn_InputPorts() const
bool isConnected_Time_OutputPort(FwIndexType portNum)
@ NUM_CYCLEIN_INPUT_PORTS
@ EVENTID_RATEGROUPSTARTED
Informational event that rate group has started.
@ EVENTID_RATEGROUPCYCLESLIP
Warning event that rate group has had a cycle slip.
virtual ~ActiveRateGroupComponentBase()
Destroy ActiveRateGroupComponentBase object.
void RateGroupMemberOut_out(FwIndexType portNum, U32 context)
Invoke output port RateGroupMemberOut.
virtual void PingIn_handler(FwIndexType portNum, U32 key)=0
Handler for input port PingIn.
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
bool isConnected_PingOut_OutputPort(FwIndexType portNum)
ActiveRateGroupComponentBase(const char *compName="")
Construct ActiveRateGroupComponentBase object.
FwIndexType getNum_RateGroupMemberOut_OutputPorts() const
@ CHANNELID_RGMAXTIME
Channel ID for RgMaxTime.
@ CHANNELID_RGCYCLESLIPS
Channel ID for RgCycleSlips.
bool isConnected_Log_OutputPort(FwIndexType portNum)
friend class ActiveRateGroupComponentBaseFriend
Friend class for white-box testing.
void log_WARNING_HI_RateGroupCycleSlip(U32 cycle)
FwIndexType getNum_PingOut_OutputPorts() const
Svc::InputPingPort * get_PingIn_InputPort(FwIndexType portNum)
@ NUM_PINGOUT_OUTPUT_PORTS
@ NUM_RATEGROUPMEMBEROUT_OUTPUT_PORTS
virtual void PingIn_preMsgHook(FwIndexType portNum, U32 key)
Pre-message hook for async input port PingIn.
void set_Time_OutputPort(FwIndexType portNum, Fw::InputTimePort *port)
Connect port to Time[portNum].
bool isConnected_RateGroupMemberOut_OutputPort(FwIndexType portNum)
void log_DIAGNOSTIC_RateGroupStarted()
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
virtual void CycleIn_preMsgHook(FwIndexType portNum, Os::RawTime &cycleStart)
Pre-message hook for async input port CycleIn.
void set_RateGroupMemberOut_OutputPort(FwIndexType portNum, Svc::InputSchedPort *port)
Connect port to RateGroupMemberOut[portNum].
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
void PingIn_handlerBase(FwIndexType portNum, U32 key)
Handler base-class function for input port PingIn.
void set_Tlm_OutputPort(FwIndexType portNum, Fw::InputTlmPort *port)
Connect port to Tlm[portNum].
void set_Log_OutputPort(FwIndexType portNum, Fw::InputLogPort *port)
Connect port to Log[portNum].
FwIndexType getNum_Tlm_OutputPorts() const
void PingOut_out(FwIndexType portNum, U32 key)
Invoke output port PingOut.